The present invention relates to an image processing apparatus and an image processing method which process digitized image data, and more particularly to an image processing apparatus and an image processing method in which plural component functional image processing modules are prepared and various image processing functions are realized by combining the modules.
A technique in which plural component functional image processing modules are prepared and various image processing functions are realized by combining the modules is used in many systems which handle a digital image, such as a document editor, a drawing tool, an image transmission apparatus, and a printer.
In a DTP (Desk Top Publishing) system into which an image can be input, a print system which can output an image, or the like, various image processes such as enlargement/reduction, rotation, affine transformation, color conversion, filter, and combination are performed on an image to be processed. When such a process is to be performed, the process is sometimes performed by using a dedicated hardware in the case where the attribute of an input image, the process contents, the procedure, parameters, and the like are fixed. In the case where various images of different color spaces or bit numbers per pixel are input, or where the process contents, the procedure, parameters, and the like are variously changed, however, such images or changes must be handled by a more flexible configuration.
As means which can satisfy such a requirement, conventionally, a technique is proposed in which programmable modules are connected in a pipeline manner or a DAG (Directed Acyclic Graph) manner, so that a desired process is flexibly performed (for example, see the Unexamined Japanese Patent Application Nos. Hei5-260373 and Hei7-105020).
The Unexamined Japanese Patent Application No. Hei5-260373 discloses a digital video signal processing apparatus which is configured so that contents of calculation processes of plural programmable calculation processing sections, and the connection manner of the programmable calculation processing sections through a network section can be set freely from the outside through a host controlling section, whereby a high-speed sophisticated calculation process is enabled, and the degree of freedom in change of a function or a system is made higher. The Unexamined Japanese Patent Application No. Hei7-105020 discloses a pipelined image processing system in which necessary functional modules are connected/initialized in pipeline manner in a desired sequence to perform a process, whereby the image processing can be flexibly performed.
In the technique disclosed in the Unexamined Japanese Patent Application No. Hei7-105020, a simulation system of a multiprocess pipeline by a single processor which is used in an operating system such as UNIX (registered trademark) is applied to an image processing field or the like. In image processing, particularly, when one process unit is restricted to a part of an image, for example, one line of an image, memory areas which are respectively held for processing by processing modules can be remarkably reduced.
As a result, an image processing apparatus which can implement a complex process with a reduced memory capacity, and which has a low production cost can be provided. When such an apparatus is operated on an operating system supporting virtual storage, swap-out due to an insufficient memory capacity is suppressed to a minimum level, and hence the apparatus can implement a process at a high speed.
In the case where an image processing apparatus which can perform a desired complex process as described above is configured by arbitrarily combining component functional modules, a very important function is reinitialization in which the state is returned to the initial state so that a predetermined process is again performed with being started from the beginning of image data to be processed. Many pipeline processes can be performed from beginning to end without activating reinitialization. However, reinitialization must be activated in a pipeline process such as described below.
As shown in FIG. 8, for example, a pipeline process includes an image inputting section 102, a histogram producing section 103, and a binarizing section 104. Digital image data supplied from an image storing section 101 is binarized, and the binarized data is supplied to an image outputting section. In the pipeline process, it is assumed that histogram data of an image to be processed is produced by the histogram producing section 103, a binarization threshold is determined with using the histogram data, and the binarizing section 104 performs a binarizing process based on the binarization threshold.
Since, in order to produce a histogram in the histogram producing section 103, all pixel values of the image to be processed are necessary, it is required to read image data of all lines and obtain information of all pixels. In the above-described pipeline process of the conventional art, either of the following two systems may be employed in order to realize a process of reading image data of all lines and obtaining information of all pixels.
In the first one of the systems, as shown in FIG. 9, separate pipelines, or a pipeline 200A which produces histogram data, and a pipeline 200B which performs a binarizing process on the basis of the produced histogram data. Assuming a case where this system is realized as a process program module on a computer, the image inputting section 102 is twice produced, and the initializing process in the image inputting section 102 is twice performed. Therefore, the resource and the processing speed are wasted.
In the second system, the histogram producing section 103 in the single pipeline shown in FIG. 8 is configured as shown in FIG. 10. Specifically, the histogram producing section 103 is configured so as to have an input buffer 301 which holds all lines of image data supplied from a preceding module, an output buffer 302 which outputs a process result to a module in a succeeding stage, and a histogram production controller 303 which controls the histogram producing process.
Assuming a case where this system is realized as a process program module on a computer, in the histogram producing section 103, all image data which are supplied form the preceding module in initialization are first stored into the input buffer 301. Next, the histogram production controller 303 produces histogram data with using the all image data stored in the input buffer 301, and initializes (=1) a line counter which is internally held. When the output buffer 302 is transferred from the succeeding module and an output request is received, the histogram production controller 303 copies the image data held in the input buffer 301, into the output buffer 302 by unit of line, returns the output buffer 302 to the succeeding stage, and then increments the line counter by 1.
In the second system, although conversion of image data is not performed at all in the histogram producing process of the histogram producing section 103, it is required to hold all of input image data. Therefore, a buffer having a memory capacity by which all image data can be stored is necessary as the input buffer 301. As a result, the resource is largely wasted.